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-rw-r--r--main/linux-vanilla/0001-Add-dts-for-GIGABYTE-X-Gene-MP30-AR0.patch786
1 files changed, 786 insertions, 0 deletions
diff --git a/main/linux-vanilla/0001-Add-dts-for-GIGABYTE-X-Gene-MP30-AR0.patch b/main/linux-vanilla/0001-Add-dts-for-GIGABYTE-X-Gene-MP30-AR0.patch
new file mode 100644
index 0000000000..b22d04ec17
--- /dev/null
+++ b/main/linux-vanilla/0001-Add-dts-for-GIGABYTE-X-Gene-MP30-AR0.patch
@@ -0,0 +1,786 @@
+From e9614bce69232e6e571a706d8744198d284c0789 Mon Sep 17 00:00:00 2001
+From: Carlo Landmeter <clandmeter@gmail.com>
+Date: Fri, 5 Aug 2016 14:00:54 +0000
+Subject: [PATCH] Add dts for GIGABYTE X-Gene MP30-AR0
+
+---
+ arch/arm64/boot/dts/apm/Makefile | 1 +
+ arch/arm64/boot/dts/apm/apm-mp30ar0.dts | 179 +++++++++++++++++
+ arch/arm64/boot/dts/apm/apm-storm.dtsi | 336 +++++++++++++++++++++++++++++---
+ 3 files changed, 485 insertions(+), 31 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/apm/apm-mp30ar0.dts
+
+diff --git a/arch/arm64/boot/dts/apm/Makefile b/arch/arm64/boot/dts/apm/Makefile
+index c75f17a4..2582444 100644
+--- a/arch/arm64/boot/dts/apm/Makefile
++++ b/arch/arm64/boot/dts/apm/Makefile
+@@ -1,5 +1,6 @@
+ dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
+ dtb-$(CONFIG_ARCH_XGENE) += apm-merlin.dtb
++dtb-$(CONFIG_ARCH_XGENE) += apm-mp30ar0.dtb
+
+ always := $(dtb-y)
+ subdir-y := $(dts-dirs)
+diff --git a/arch/arm64/boot/dts/apm/apm-mp30ar0.dts b/arch/arm64/boot/dts/apm/apm-mp30ar0.dts
+new file mode 100644
+index 0000000..841e614
+--- /dev/null
++++ b/arch/arm64/boot/dts/apm/apm-mp30ar0.dts
+@@ -0,0 +1,179 @@
++/*
++ * dts file for AppliedMicro (APM) Mustang Board
++ *
++ * Copyright (C) 2013, Applied Micro Circuits Corporation
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++/dts-v1/;
++
++/include/ "apm-storm.dtsi"
++
++/ {
++ model = "Gigabyte X-Gene MP30-AR0 board";
++ compatible = "apm,mustang", "apm,xgene-storm";
++
++ chosen { };
++
++ aliases {
++ ethernet0 = &sgenet0;
++ };
++
++ memory {
++ device_type = "memory";
++ reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
++ };
++
++ poweroff_mbox: poweroff_mbox@10548000 {
++ compatible = "syscon";
++ reg = <0x0 0x10548000 0x0 0x30>;
++ };
++
++ poweroff: poweroff@10548010 {
++ compatible = "syscon-poweroff";
++ regmap = <&poweroff_mbox>;
++ offset = <0x10>;
++ mask = <0x1>;
++ };
++
++ cpus {
++ cpu@000 {
++ cpu-release-addr = <0x0 0x80008008>;
++ };
++ cpu@001 {
++ cpu-release-addr = <0x0 0x80009008>;
++ };
++ cpu@100 {
++ cpu-release-addr = <0x0 0x8000A008>;
++ };
++ cpu@101 {
++ cpu-release-addr = <0x0 0x8000B008>;
++ };
++ cpu@200 {
++ cpu-release-addr = <0x0 0x8000C008>;
++ };
++ cpu@201 {
++ cpu-release-addr = <0x0 0x8000D008>;
++ };
++ cpu@300 {
++ cpu-release-addr = <0x0 0x8000E008>;
++ };
++ cpu@301 {
++ cpu-release-addr = <0x0 0x8000F008>;
++ };
++ };
++};
++
++/delete-node/&sataphy2clk;
++/delete-node/&sataphy3clk;
++/delete-node/&sata23clk;
++/delete-node/&sata45clk;
++
++&phy2 {
++ /delete-property/clocks;
++};
++
++&phy3 {
++ /delete-property/clocks;
++};
++
++&sata2 {
++ /delete-property/clocks;
++ /delete-property/phys;
++ /delete-property/phy-names;
++};
++
++&sata3 {
++ /delete-property/clocks;
++ /delete-property/phys;
++ /delete-property/phy-names;
++};
++
++&pcie0clk {
++ status = "ok";
++};
++
++&pcie0 {
++ status = "ok";
++};
++
++&pcie2clk {
++ status = "ok";
++};
++
++&pcie2 {
++ status = "ok";
++};
++
++&pcie3clk {
++ status = "ok";
++};
++
++&pcie3 {
++ status = "ok";
++};
++
++&serial0 {
++ clock-frequency = <50000000>;
++ status = "ok";
++};
++
++&serial1 {
++ clock-frequency = <50000000>;
++ status = "ok";
++};
++
++&serial2 {
++ clock-frequency = <50000000>;
++ status = "ok";
++};
++
++&serial3 {
++ clock-frequency = <50000000>;
++ status = "ok";
++};
++
++&menet {
++ status = "disabled";
++};
++
++&sgenet0 {
++ status = "ok";
++};
++
++&sgenet1 {
++ status = "ok";
++};
++
++&xgenet {
++ status = "ok";
++ sfp-gpios = <&sbgpio 12 1>;
++ rxlos-gpios = <&sbgpio 9 1>;
++};
++
++&xgenet1 {
++ status = "ok";
++ sfp-gpios = <&sbgpio 13 1>;
++ rxlos-gpios = <&sbgpio 11 1>;
++};
++
++&sbgpio {
++ interrupts = <0x0 0x28 0x1>,
++ <0x0 0x2a 0x1>;
++};
++
++&mmc0 {
++ status = "ok";
++};
++
++&usb0 {
++ status = "ok";
++};
++
++&usb1 {
++ status = "ok";
++};
+diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
+index 6c5ed11..4cfd5c0 100644
+--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
++++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
+@@ -25,6 +25,7 @@
+ reg = <0x0 0x000>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_0>;
+ };
+ cpu@001 {
+ device_type = "cpu";
+@@ -32,6 +33,7 @@
+ reg = <0x0 0x001>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_0>;
+ };
+ cpu@100 {
+ device_type = "cpu";
+@@ -39,6 +41,7 @@
+ reg = <0x0 0x100>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_1>;
+ };
+ cpu@101 {
+ device_type = "cpu";
+@@ -46,6 +49,7 @@
+ reg = <0x0 0x101>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_1>;
+ };
+ cpu@200 {
+ device_type = "cpu";
+@@ -53,6 +57,7 @@
+ reg = <0x0 0x200>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_2>;
+ };
+ cpu@201 {
+ device_type = "cpu";
+@@ -60,6 +65,7 @@
+ reg = <0x0 0x201>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_2>;
+ };
+ cpu@300 {
+ device_type = "cpu";
+@@ -67,6 +73,7 @@
+ reg = <0x0 0x300>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_3>;
+ };
+ cpu@301 {
+ device_type = "cpu";
+@@ -74,6 +81,19 @@
+ reg = <0x0 0x301>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x1 0x0000fff8>;
++ next-level-cache = <&xgene_L2_3>;
++ };
++ xgene_L2_0: l2-cache-0 {
++ compatible = "cache";
++ };
++ xgene_L2_1: l2-cache-1 {
++ compatible = "cache";
++ };
++ xgene_L2_2: l2-cache-2 {
++ compatible = "cache";
++ };
++ xgene_L2_3: l2-cache-3 {
++ compatible = "cache";
+ };
+ };
+
+@@ -81,10 +101,10 @@
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+- reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */
+- <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */
+- <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */
+- <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */
++ reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */
++ <0x0 0x780a0000 0x0 0x20000>, /* GIC CPU */
++ <0x0 0x780c0000 0x0 0x10000>, /* GIC VCPU Control */
++ <0x0 0x780e0000 0x0 0x20000>; /* GIC VCPU */
+ interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */
+ };
+
+@@ -98,7 +118,7 @@
+ };
+
+ pmu {
+- compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
++ compatible = "apm,potenza-pmu", "arm,armv8-pmuv3", "apm,xgene-pmu-v2";
+ interrupts = <1 12 0xff04>;
+ };
+
+@@ -150,14 +170,33 @@
+ clock-output-names = "socplldiv2";
+ };
+
+- qmlclk: qmlclk {
++ ahbclk: ahbclk@17000000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+- clock-names = "qmlclk";
+- reg = <0x0 0x1703C000 0x0 0x1000>;
+- reg-names = "csr-reg";
+- clock-output-names = "qmlclk";
++ reg = <0x0 0x17000000 0x0 0x2000>;
++ reg-names = "div-reg";
++ divider-offset = <0x164>;
++ divider-width = <0x5>;
++ divider-shift = <0x0>;
++ clock-output-names = "ahbclk";
++ };
++
++ sdioclk: sdioclk@1f2ac000 {
++ compatible = "apm,xgene-device-clock";
++ #clock-cells = <1>;
++ clocks = <&socplldiv2 0>;
++ reg = <0x0 0x1f2ac000 0x0 0x1000
++ 0x0 0x17000000 0x0 0x2000>;
++ reg-names = "csr-reg", "div-reg";
++ csr-offset = <0x0>;
++ csr-mask = <0x2>;
++ enable-offset = <0x8>;
++ enable-mask = <0x2>;
++ divider-offset = <0x178>;
++ divider-width = <0x8>;
++ divider-shift = <0x0>;
++ clock-output-names = "sdioclk";
+ };
+
+ ethclk: ethclk {
+@@ -177,7 +216,8 @@
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&ethclk 0>;
+- reg = <0x0 0x1702C000 0x0 0x1000>;
++ clock-names = "menetclk";
++ reg = <0x0 0x1702c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "menetclk";
+ };
+@@ -388,11 +428,21 @@
+ reg-names = "csr-reg";
+ clock-output-names = "dmaclk";
+ };
++
++ cryptoclk: cryptoclk@1f25c000 {
++ compatible = "apm,xgene-device-clock";
++ #clock-cells = <1>;
++ clocks = <&socplldiv2 0>;
++ reg = <0x0 0x1f25c000 0x0 0x1000>;
++ reg-names = "csr-reg";
++ clock-output-names = "cryptoclk";
++ };
+ };
+
+ msi: msi@79000000 {
+- compatible = "apm,xgene1-msi";
++ compatible = "xgene,gic-msi", "apm,xgene1-msi";
+ msi-controller;
++ msi-available-ranges = <0x0 0x1000>;
+ reg = <0x00 0x79000000 0x0 0x900000>;
+ interrupts = < 0x0 0x10 0x4
+ 0x0 0x11 0x4
+@@ -444,6 +494,11 @@
+ reg = <0x0 0x1054a000 0x0 0x20>;
+ };
+
++ rb: rb@7e000000 {
++ compatible = "apm,xgene-rb", "syscon";
++ reg = <0x0 0x7e000000 0x0 0x10>;
++ };
++
+ edac@78800000 {
+ compatible = "apm,xgene-edac";
+ #address-cells = <2>;
+@@ -453,6 +508,7 @@
+ regmap-mcba = <&mcba>;
+ regmap-mcbb = <&mcbb>;
+ regmap-efuse = <&efuse>;
++ regmap-rb = <&rb>;
+ reg = <0x0 0x78800000 0x0 0x100>;
+ interrupts = <0x0 0x20 0x4>,
+ <0x0 0x21 0x4>,
+@@ -517,6 +573,64 @@
+ };
+ };
+
++ pmu: pmu@78810000 {
++ compatible = "apm,xgene-pmu-v2";
++ #address-cells = <2>;
++ #size-cells = <2>;
++ ranges;
++ regmap-csw = <&csw>;
++ regmap-mcba = <&mcba>;
++ regmap-mcbb = <&mcbb>;
++ reg = <0x0 0x78810000 0x0 0x1000>;
++ interrupts = <0x0 0x22 0x4>;
++ };
++
++ pmul3c@7e610000 {
++ compatible = "apm,xgene-pmu-l3c";
++ reg = <0x0 0x7e610000 0x0 0x1000>;
++ };
++
++ pmuiob@7e940000 {
++ compatible = "apm,xgene-pmu-iob";
++ reg = <0x0 0x7e940000 0x0 0x1000>;
++ };
++
++ pmucmcb@7e710000 {
++ compatible = "apm,xgene-pmu-mcb";
++ reg = <0x0 0x7e710000 0x0 0x1000>;
++ memory-controller-bridge = <0>;
++ };
++
++ pmucmcb@7e730000 {
++ compatible = "apm,xgene-pmu-mcb";
++ reg = <0x0 0x7e730000 0x0 0x1000>;
++ memory-controller-bridge = <1>;
++ };
++
++ pmucmc@7e810000 {
++ compatible = "apm,xgene-pmu-mc";
++ reg = <0x0 0x7e810000 0x0 0x1000>;
++ memory-controller = <0>;
++ };
++
++ pmucmc@7e850000 {
++ compatible = "apm,xgene-pmu-mc";
++ reg = <0x0 0x7e850000 0x0 0x1000>;
++ memory-controller = <1>;
++ };
++
++ pmucmc@7e890000 {
++ compatible = "apm,xgene-pmu-mc";
++ reg = <0x0 0x7e890000 0x0 0x1000>;
++ memory-controller = <2>;
++ };
++
++ pmucmc@7e8d0000 {
++ compatible = "apm,xgene-pmu-mc";
++ reg = <0x0 0x7e8d0000 0x0 0x1000>;
++ memory-controller = <3>;
++ };
++
+ pcie0: pcie@1f2b0000 {
+ status = "disabled";
+ device_type = "pci";
+@@ -532,6 +646,8 @@
+ 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */
+ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
++ ib-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000 /* dma */
++ 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1
+ 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1
+@@ -557,6 +673,8 @@
+ 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */
+ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
++ ib-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000 /* dma */
++ 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1
+ 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1
+@@ -582,6 +700,8 @@
+ 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */
+ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
++ ib-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000 /* dma */
++ 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1
+ 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1
+@@ -607,6 +727,8 @@
+ 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */
+ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
++ ib-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000 /* dma */
++ 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1
+ 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1
+@@ -632,6 +754,8 @@
+ 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */
+ dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
+ 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>;
++ ib-ranges = <0x42000000 0x40 0x00000000 0x40 0x00000000 0x40 0x00000000 /* dma */
++ 0x00000000 0x0 0x79000000 0x00 0x79000000 0x0 0x00800000>; /* msi */
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1
+ 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1
+@@ -642,6 +766,30 @@
+ msi-parent = <&msi>;
+ };
+
++ mailbox: mailbox@10540000 {
++ compatible = "apm,xgene-slimpro-mbox";
++ reg = <0x0 0x10540000 0x0 0xa000>;
++ #mbox-cells = <1>;
++ interrupts = <0x0 0x0 0x4>,
++ <0x0 0x1 0x4>,
++ <0x0 0x2 0x4>,
++ <0x0 0x3 0x4>,
++ <0x0 0x4 0x4>,
++ <0x0 0x5 0x4>,
++ <0x0 0x6 0x4>,
++ <0x0 0x7 0x4>;
++ };
++
++ i2cslimpro {
++ compatible = "apm,xgene-slimpro-i2c";
++ mboxes = <&mailbox 0>;
++ };
++
++ hwmonslimpro {
++ compatible = "apm,xgene-slimpro-hwmon";
++ mboxes = <&mailbox 7>;
++ };
++
+ serial0: serial@1c020000 {
+ status = "disabled";
+ device_type = "serial";
+@@ -686,6 +834,62 @@
+ interrupts = <0x0 0x4f 0x4>;
+ };
+
++ mmc0: mmc@1c000000 {
++ status = "disabled";
++ compatible = "apm,xgene-sdhci", "arasan,sdhci-4.9a";
++ reg = <0x0 0x1c000000 0x0 0x100>;
++ interrupts = <0x0 0x49 0x4>;
++ dma-coherent;
++ no-1-8-v;
++ clock-names = "clk_xin", "clk_ahb";
++ clocks = <&sdioclk 0>, <&ahbclk 0>;
++ };
++
++ mmc1: mmc@1c000100 {
++ status = "disabled";
++ compatible = "apm,xgene-sdhci", "arasan,sdhci-4.9a";
++ reg = <0x0 0x1c000100 0x0 0x100>;
++ interrupts = <0x0 0x49 0x4>;
++ dma-coherent;
++ no-1-8-v;
++ clock-names = "clk_xin", "clk_ahb";
++ clocks = <&sdioclk 0>, <&ahbclk 0>;
++ };
++
++ gfcgpio: gpio0@1701c000 {
++ compatible = "apm,xgene-gpio";
++ reg = <0x0 0x1701c000 0x0 0x40>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ dwgpio: gpio@1c024000 {
++ compatible = "snps,dw-apb-gpio";
++ reg = <0x0 0x1c024000 0x0 0x1000>;
++ reg-io-width = <4>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ porta: gpio-controller@0 {
++ compatible = "snps,dw-apb-gpio-port";
++ gpio-controller;
++ snps,nr-gpios = <32>;
++ reg = <0>;
++ };
++ };
++
++ i2c0: i2c@10512000 {
++ status = "disabled";
++ #address-cells = <1>;
++ #size-cells = <0>;
++ compatible = "snps,designware-i2c";
++ reg = <0x0 0x10512000 0x0 0x1000>;
++ interrupts = <0 0x44 0x4>;
++ #clock-cells = <1>;
++ clocks = <&ahbclk 0>;
++ bus_num = <0>;
++ };
++
+ phy1: phy@1f21a000 {
+ compatible = "apm,xgene-phy";
+ reg = <0x0 0x1f21a000 0x0 0x100>;
+@@ -760,7 +964,26 @@
+ phy-names = "sata-phy";
+ };
+
+- sbgpio: sbgpio@17001000{
++ /* Do not change dwusb name, coded for backward compatibility */
++ usb0: dwusb@19000000 {
++ status = "disabled";
++ compatible = "xhci-platform";
++ reg = <0x0 0x19000000 0x0 0x100000>;
++ interrupts = <0x0 0x89 0x4>;
++ dma-coherent;
++ dr_mode = "host";
++ };
++
++ usb1: dwusb@19800000 {
++ status = "disabled";
++ compatible = "xhci-platform";
++ reg = <0x0 0x19800000 0x0 0x100000>;
++ interrupts = <0x0 0x8a 0x4>;
++ dma-coherent;
++ dr_mode = "host";
++ };
++
++ sbgpio: gpio@17001000{
+ compatible = "apm,xgene-gpio-sb";
+ reg = <0x0 0x17001000 0x0 0x400>;
+ #gpio-cells = <2>;
+@@ -771,6 +994,9 @@
+ <0x0 0x2b 0x1>,
+ <0x0 0x2c 0x1>,
+ <0x0 0x2d 0x1>;
++ interrupt-parent = <&gic>;
++ #interrupt-cells = <2>;
++ interrupt-controller;
+ };
+
+ rtc: rtc@10510000 {
+@@ -785,8 +1011,8 @@
+ compatible = "apm,xgene-enet";
+ status = "disabled";
+ reg = <0x0 0x17020000 0x0 0xd100>,
+- <0x0 0X17030000 0x0 0Xc300>,
+- <0x0 0X10000000 0x0 0X200>;
++ <0x0 0x17030000 0x0 0xc300>,
++ <0x0 0x10000000 0x0 0x200>;
+ reg-names = "enet_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0x3c 0x4>;
+ dma-coherent;
+@@ -803,7 +1029,6 @@
+ compatible = "ethernet-phy-id001c.c915";
+ reg = <0x3>;
+ };
+-
+ };
+ };
+
+@@ -811,11 +1036,17 @@
+ compatible = "apm,xgene1-sgenet";
+ status = "disabled";
+ reg = <0x0 0x1f210000 0x0 0xd100>,
+- <0x0 0x1f200000 0x0 0Xc300>,
+- <0x0 0x1B000000 0x0 0X200>;
++ <0x0 0x1f200000 0x0 0xc300>,
++ <0x0 0x1b000000 0x0 0x200>;
+ reg-names = "enet_csr", "ring_csr", "ring_cmd";
+- interrupts = <0x0 0xA0 0x4>,
+- <0x0 0xA1 0x4>;
++ interrupts = <0x0 0xa0 0x4>,
++ <0x0 0xa1 0x4>,
++ <0x0 0xa2 0x4>,
++ <0x0 0xa3 0x4>,
++ <0x0 0xa4 0x4>,
++ <0x0 0xa5 0x4>,
++ <0x0 0xa6 0x4>,
++ <0x0 0xa7 0x4>;
+ dma-coherent;
+ clocks = <&sge0clk 0>;
+ local-mac-address = [00 00 00 00 00 00];
+@@ -826,11 +1057,17 @@
+ compatible = "apm,xgene1-sgenet";
+ status = "disabled";
+ reg = <0x0 0x1f210030 0x0 0xd100>,
+- <0x0 0x1f200000 0x0 0Xc300>,
+- <0x0 0x1B000000 0x0 0X8000>;
++ <0x0 0x1f200000 0x0 0xc300>,
++ <0x0 0x1b000000 0x0 0x8000>;
+ reg-names = "enet_csr", "ring_csr", "ring_cmd";
+- interrupts = <0x0 0xAC 0x4>,
+- <0x0 0xAD 0x4>;
++ interrupts = <0x0 0xac 0x4>,
++ <0x0 0xad 0x4>,
++ <0x0 0xae 0x4>,
++ <0x0 0xaf 0x4>,
++ <0x0 0xb0 0x4>,
++ <0x0 0xb1 0x4>,
++ <0x0 0xb2 0x4>,
++ <0x0 0xb3 0x4>;
+ port-id = <1>;
+ dma-coherent;
+ clocks = <&sge1clk 0>;
+@@ -842,11 +1079,18 @@
+ compatible = "apm,xgene1-xgenet";
+ status = "disabled";
+ reg = <0x0 0x1f610000 0x0 0xd100>,
+- <0x0 0x1f600000 0x0 0Xc300>,
+- <0x0 0x18000000 0x0 0X200>;
++ <0x0 0x1f600000 0x0 0xc300>,
++ <0x0 0x18000000 0x0 0x200>;
+ reg-names = "enet_csr", "ring_csr", "ring_cmd";
+ interrupts = <0x0 0x60 0x4>,
+- <0x0 0x61 0x4>;
++ <0x0 0x61 0x4>,
++ <0x0 0x62 0x4>,
++ <0x0 0x63 0x4>,
++ <0x0 0x64 0x4>,
++ <0x0 0x65 0x4>,
++ <0x0 0x66 0x4>,
++ <0x0 0x67 0x4>;
++ channel = <0>;
+ dma-coherent;
+ clocks = <&xge0clk 0>;
+ /* mac address will be overwritten by the bootloader */
+@@ -858,11 +1102,17 @@
+ compatible = "apm,xgene1-xgenet";
+ status = "disabled";
+ reg = <0x0 0x1f620000 0x0 0xd100>,
+- <0x0 0x1f600000 0x0 0Xc300>,
+- <0x0 0x18000000 0x0 0X8000>;
++ <0x0 0x1f600000 0x0 0xc300>,
++ <0x0 0x18000000 0x0 0x8000>;
+ reg-names = "enet_csr", "ring_csr", "ring_cmd";
+- interrupts = <0x0 0x6C 0x4>,
+- <0x0 0x6D 0x4>;
++ interrupts = <0x0 0x6c 0x4>,
++ <0x0 0x6d 0x4>,
++ <0x0 0x6e 0x4>,
++ <0x0 0x6f 0x4>,
++ <0x0 0x70 0x4>,
++ <0x0 0x71 0x4>,
++ <0x0 0x72 0x4>,
++ <0x0 0x73 0x4>;
+ port-id = <1>;
+ dma-coherent;
+ clocks = <&xge1clk 0>;
+@@ -893,5 +1143,29 @@
+ dma-coherent;
+ clocks = <&dmaclk 0>;
+ };
++
++ crypto: crypto@1f250000 {
++ device_type = "crypto";
++ compatible = "apm,xgene-crypto-v1";
++ status = "ok";
++ reg = <0x0 0x1f250000 0x0 0x10000>,
++ <0x0 0x1f200000 0x0 0X10000>,
++ <0x0 0x1b00a000 0x0 0x02000>,
++ <0x0 0x1054a000 0x0 0x0001c>;
++ dma-coherent;
++ clocks = <&cryptoclk 0>;
++ interrupts = <0x0 0x85 0x4>,
++ <0x0 0xbc 0x4>,
++ <0x0 0xbd 0x4>;
++ };
++
++ pka: pka@10524000 {
++ device_type = "pka";
++ compatible = "apm,xgene-pka";
++ reg = <0x0 0x10524000 0x0 0x4000>;
++ interrupts = <0x0 0x43 0x4>;
++ clocks = <&rngpkaclk 0>;
++ };
++
+ };
+ };
+--
+2.9.1
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-03 23:24:13 +0000