From dc1d93ea8dc61686364e2659c1ac1392681b64b4 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Thu, 30 Mar 2017 12:00:10 +0200 Subject: [PATCH] ASoC: meson: add register definitions Add the register definition for the AIU and AUDIN blocks Signed-off-by: Jerome Brunet --- sound/soc/meson/aiu-regs.h | 182 +++++++++++++++++++++++++++++++++++++++++++ sound/soc/meson/audin-regs.h | 148 +++++++++++++++++++++++++++++++++++ 2 files changed, 330 insertions(+) create mode 100644 sound/soc/meson/aiu-regs.h create mode 100644 sound/soc/meson/audin-regs.h diff --git a/sound/soc/meson/aiu-regs.h b/sound/soc/meson/aiu-regs.h new file mode 100644 index 0000000..67391e6 --- /dev/null +++ b/sound/soc/meson/aiu-regs.h @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2017 BayLibre, SAS + * Author: Jerome Brunet + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef _AIU_REGS_H_ +#define _AIU_REGS_H_ + +#define AIU_958_BPF 0x000 +#define AIU_958_BRST 0x004 +#define AIU_958_LENGTH 0x008 +#define AIU_958_PADDSIZE 0x00C +#define AIU_958_MISC 0x010 +#define AIU_958_FORCE_LEFT 0x014 /* Unknown */ +#define AIU_958_DISCARD_NUM 0x018 +#define AIU_958_DCU_FF_CTRL 0x01C +#define AIU_958_CHSTAT_L0 0x020 +#define AIU_958_CHSTAT_L1 0x024 +#define AIU_958_CTRL 0x028 +#define AIU_958_RPT 0x02C +#define AIU_I2S_MUTE_SWAP 0x030 +#define AIU_I2S_SOURCE_DESC 0x034 +#define AIU_I2S_MED_CTRL 0x038 +#define AIU_I2S_MED_THRESH 0x03C +#define AIU_I2S_DAC_CFG 0x040 +#define AIU_I2S_SYNC 0x044 /* Unknown */ +#define AIU_I2S_MISC 0x048 +#define AIU_I2S_OUT_CFG 0x04C +#define AIU_I2S_FF_CTRL 0x050 /* Unknown */ +#define AIU_RST_SOFT 0x054 +#define AIU_CLK_CTRL 0x058 +#define AIU_MIX_ADCCFG 0x05C +#define AIU_MIX_CTRL 0x060 +#define AIU_CLK_CTRL_MORE 0x064 +#define AIU_958_POP 0x068 +#define AIU_MIX_GAIN 0x06C +#define AIU_958_SYNWORD1 0x070 +#define AIU_958_SYNWORD2 0x074 +#define AIU_958_SYNWORD3 0x078 +#define AIU_958_SYNWORD1_MASK 0x07C +#define AIU_958_SYNWORD2_MASK 0x080 +#define AIU_958_SYNWORD3_MASK 0x084 +#define AIU_958_FFRDOUT_THD 0x088 +#define AIU_958_LENGTH_PER_PAUSE 0x08C +#define AIU_958_PAUSE_NUM 0x090 +#define AIU_958_PAUSE_PAYLOAD 0x094 +#define AIU_958_AUTO_PAUSE 0x098 +#define AIU_958_PAUSE_PD_LENGTH 0x09C +#define AIU_CODEC_DAC_LRCLK_CTRL 0x0A0 +#define AIU_CODEC_ADC_LRCLK_CTRL 0x0A4 +#define AIU_HDMI_CLK_DATA_CTRL 0x0A8 +#define AIU_CODEC_CLK_DATA_CTRL 0x0AC +#define AIU_ACODEC_CTRL 0x0B0 +#define AIU_958_CHSTAT_R0 0x0C0 +#define AIU_958_CHSTAT_R1 0x0C4 +#define AIU_958_VALID_CTRL 0x0C8 +#define AIU_AUDIO_AMP_REG0 0x0F0 /* Unknown */ +#define AIU_AUDIO_AMP_REG1 0x0F4 /* Unknown */ +#define AIU_AUDIO_AMP_REG2 0x0F8 /* Unknown */ +#define AIU_AUDIO_AMP_REG3 0x0FC /* Unknown */ +#define AIU_AIFIFO2_CTRL 0x100 +#define AIU_AIFIFO2_STATUS 0x104 +#define AIU_AIFIFO2_GBIT 0x108 +#define AIU_AIFIFO2_CLB 0x10C +#define AIU_CRC_CTRL 0x110 +#define AIU_CRC_STATUS 0x114 +#define AIU_CRC_SHIFT_REG 0x118 +#define AIU_CRC_IREG 0x11C +#define AIU_CRC_CAL_REG1 0x120 +#define AIU_CRC_CAL_REG0 0x124 +#define AIU_CRC_POLY_COEF1 0x128 +#define AIU_CRC_POLY_COEF0 0x12C +#define AIU_CRC_BIT_SIZE1 0x130 +#define AIU_CRC_BIT_SIZE0 0x134 +#define AIU_CRC_BIT_CNT1 0x138 +#define AIU_CRC_BIT_CNT0 0x13C +#define AIU_AMCLK_GATE_HI 0x140 +#define AIU_AMCLK_GATE_LO 0x144 +#define AIU_AMCLK_MSR 0x148 +#define AIU_AUDAC_CTRL0 0x14C /* Unknown */ +#define AIU_DELTA_SIGMA0 0x154 /* Unknown */ +#define AIU_DELTA_SIGMA1 0x158 /* Unknown */ +#define AIU_DELTA_SIGMA2 0x15C /* Unknown */ +#define AIU_DELTA_SIGMA3 0x160 /* Unknown */ +#define AIU_DELTA_SIGMA4 0x164 /* Unknown */ +#define AIU_DELTA_SIGMA5 0x168 /* Unknown */ +#define AIU_DELTA_SIGMA6 0x16C /* Unknown */ +#define AIU_DELTA_SIGMA7 0x170 /* Unknown */ +#define AIU_DELTA_SIGMA_LCNTS 0x174 /* Unknown */ +#define AIU_DELTA_SIGMA_RCNTS 0x178 /* Unknown */ +#define AIU_MEM_I2S_START_PTR 0x180 +#define AIU_MEM_I2S_RD_PTR 0x184 +#define AIU_MEM_I2S_END_PTR 0x188 +#define AIU_MEM_I2S_MASKS 0x18C +#define AIU_MEM_I2S_CONTROL 0x190 +#define AIU_MEM_IEC958_START_PTR 0x194 +#define AIU_MEM_IEC958_RD_PTR 0x198 +#define AIU_MEM_IEC958_END_PTR 0x19C +#define AIU_MEM_IEC958_MASKS 0x1A0 +#define AIU_MEM_IEC958_CONTROL 0x1A4 +#define AIU_MEM_AIFIFO2_START_PTR 0x1A8 +#define AIU_MEM_AIFIFO2_CURR_PTR 0x1AC +#define AIU_MEM_AIFIFO2_END_PTR 0x1B0 +#define AIU_MEM_AIFIFO2_BYTES_AVAIL 0x1B4 +#define AIU_MEM_AIFIFO2_CONTROL 0x1B8 +#define AIU_MEM_AIFIFO2_MAN_WP 0x1BC +#define AIU_MEM_AIFIFO2_MAN_RP 0x1C0 +#define AIU_MEM_AIFIFO2_LEVEL 0x1C4 +#define AIU_MEM_AIFIFO2_BUF_CNTL 0x1C8 +#define AIU_MEM_I2S_MAN_WP 0x1CC +#define AIU_MEM_I2S_MAN_RP 0x1D0 +#define AIU_MEM_I2S_LEVEL 0x1D4 +#define AIU_MEM_I2S_BUF_CNTL 0x1D8 +#define AIU_MEM_I2S_BUF_WRAP_COUNT 0x1DC +#define AIU_MEM_I2S_MEM_CTL 0x1E0 +#define AIU_MEM_IEC958_MEM_CTL 0x1E4 +#define AIU_MEM_IEC958_WRAP_COUNT 0x1E8 +#define AIU_MEM_IEC958_IRQ_LEVEL 0x1EC +#define AIU_MEM_IEC958_MAN_WP 0x1F0 +#define AIU_MEM_IEC958_MAN_RP 0x1F4 +#define AIU_MEM_IEC958_LEVEL 0x1F8 +#define AIU_MEM_IEC958_BUF_CNTL 0x1FC +#define AIU_AIFIFO_CTRL 0x200 +#define AIU_AIFIFO_STATUS 0x204 +#define AIU_AIFIFO_GBIT 0x208 +#define AIU_AIFIFO_CLB 0x20C +#define AIU_MEM_AIFIFO_START_PTR 0x210 +#define AIU_MEM_AIFIFO_CURR_PTR 0x214 +#define AIU_MEM_AIFIFO_END_PTR 0x218 +#define AIU_MEM_AIFIFO_BYTES_AVAIL 0x21C +#define AIU_MEM_AIFIFO_CONTROL 0x220 +#define AIU_MEM_AIFIFO_MAN_WP 0x224 +#define AIU_MEM_AIFIFO_MAN_RP 0x228 +#define AIU_MEM_AIFIFO_LEVEL 0x22C +#define AIU_MEM_AIFIFO_BUF_CNTL 0x230 +#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 0x234 +#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 0x238 +#define AIU_MEM_AIFIFO_MEM_CTL 0x23C +#define AIFIFO_TIME_STAMP_CNTL 0x240 +#define AIFIFO_TIME_STAMP_SYNC_0 0x244 +#define AIFIFO_TIME_STAMP_SYNC_1 0x248 +#define AIFIFO_TIME_STAMP_0 0x24C +#define AIFIFO_TIME_STAMP_1 0x250 +#define AIFIFO_TIME_STAMP_2 0x254 +#define AIFIFO_TIME_STAMP_3 0x258 +#define AIFIFO_TIME_STAMP_LENGTH 0x25C +#define AIFIFO2_TIME_STAMP_CNTL 0x260 +#define AIFIFO2_TIME_STAMP_SYNC_0 0x264 +#define AIFIFO2_TIME_STAMP_SYNC_1 0x268 +#define AIFIFO2_TIME_STAMP_0 0x26C +#define AIFIFO2_TIME_STAMP_1 0x270 +#define AIFIFO2_TIME_STAMP_2 0x274 +#define AIFIFO2_TIME_STAMP_3 0x278 +#define AIFIFO2_TIME_STAMP_LENGTH 0x27C +#define IEC958_TIME_STAMP_CNTL 0x280 +#define IEC958_TIME_STAMP_SYNC_0 0x284 +#define IEC958_TIME_STAMP_SYNC_1 0x288 +#define IEC958_TIME_STAMP_0 0x28C +#define IEC958_TIME_STAMP_1 0x290 +#define IEC958_TIME_STAMP_2 0x294 +#define IEC958_TIME_STAMP_3 0x298 +#define IEC958_TIME_STAMP_LENGTH 0x29C +#define AIU_MEM_AIFIFO2_MEM_CTL 0x2A0 +#define AIU_I2S_CBUS_DDR_CNTL 0x2A4 +#define AIU_I2S_CBUS_DDR_WDATA 0x2A8 +#define AIU_I2S_CBUS_DDR_ADDR 0x2AC + +#endif /* _AIU_REGS_H_ */ diff --git a/sound/soc/meson/audin-regs.h b/sound/soc/meson/audin-regs.h new file mode 100644 index 0000000..f224610 --- /dev/null +++ b/sound/soc/meson/audin-regs.h @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2017 BayLibre, SAS + * Author: Jerome Brunet + * Copyright (C) 2017 Amlogic, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef _AUDIN_REGS_H_ +#define _AUDIN_REGS_H_ + +/* + * Note : + * Datasheet issue page 196 + * AUDIN_MUTE_VAL 0x35 => impossible: Already assigned to AUDIN_FIFO1_PTR + * AUDIN_FIFO1_PTR is more likely to be correct here since surrounding registers + * also deal with AUDIN_FIFO1 + * + * Clarification needed from Amlogic + */ + +#define AUDIN_SPDIF_MODE 0x000 +#define AUDIN_SPDIF_FS_CLK_RLTN 0x004 +#define AUDIN_SPDIF_CHNL_STS_A 0x008 +#define AUDIN_SPDIF_CHNL_STS_B 0x00C +#define AUDIN_SPDIF_MISC 0x010 +#define AUDIN_SPDIF_NPCM_PCPD 0x014 +#define AUDIN_SPDIF_END 0x03C /* Unknown */ +#define AUDIN_I2SIN_CTRL 0x040 +#define AUDIN_SOURCE_SEL 0x044 +#define AUDIN_DECODE_FORMAT 0x048 +#define AUDIN_DECODE_CONTROL_STATUS 0x04C +#define AUDIN_DECODE_CHANNEL_STATUS_A_0 0x050 +#define AUDIN_DECODE_CHANNEL_STATUS_A_1 0x054 +#define AUDIN_DECODE_CHANNEL_STATUS_A_2 0x058 +#define AUDIN_DECODE_CHANNEL_STATUS_A_3 0x05C +#define AUDIN_DECODE_CHANNEL_STATUS_A_4 0x060 +#define AUDIN_DECODE_CHANNEL_STATUS_A_5 0x064 +#define AUDIN_FIFO0_START 0x080 +#define AUDIN_FIFO0_END 0x084 +#define AUDIN_FIFO0_PTR 0x088 +#define AUDIN_FIFO0_INTR 0x08C +#define AUDIN_FIFO0_RDPTR 0x090 +#define AUDIN_FIFO0_CTRL 0x094 +#define AUDIN_FIFO0_CTRL1 0x098 +#define AUDIN_FIFO0_LVL0 0x09C +#define AUDIN_FIFO0_LVL1 0x0A0 +#define AUDIN_FIFO0_LVL2 0x0A4 +#define AUDIN_FIFO0_REQID 0x0C0 +#define AUDIN_FIFO0_WRAP 0x0C4 +#define AUDIN_FIFO1_START 0x0CC +#define AUDIN_FIFO1_END 0x0D0 +#define AUDIN_FIFO1_PTR 0x0D4 +#define AUDIN_FIFO1_INTR 0x0D8 +#define AUDIN_FIFO1_RDPTR 0x0DC +#define AUDIN_FIFO1_CTRL 0x0E0 +#define AUDIN_FIFO1_CTRL1 0x0E4 +#define AUDIN_FIFO1_LVL0 0x100 +#define AUDIN_FIFO1_LVL1 0x104 +#define AUDIN_FIFO1_LVL2 0x108 +#define AUDIN_FIFO1_REQID 0x10C +#define AUDIN_FIFO1_WRAP 0x110 +#define AUDIN_FIFO2_START 0x114 +#define AUDIN_FIFO2_END 0x118 +#define AUDIN_FIFO2_PTR 0x11C +#define AUDIN_FIFO2_INTR 0x120 +#define AUDIN_FIFO2_RDPTR 0x124 +#define AUDIN_FIFO2_CTRL 0x128 +#define AUDIN_FIFO2_CTRL1 0x12C +#define AUDIN_FIFO2_LVL0 0x130 +#define AUDIN_FIFO2_LVL1 0x134 +#define AUDIN_FIFO2_LVL2 0x138 +#define AUDIN_FIFO2_REQID 0x13C +#define AUDIN_FIFO2_WRAP 0x140 +#define AUDIN_INT_CTRL 0x144 +#define AUDIN_FIFO_INT 0x148 +#define PCMIN_CTRL0 0x180 +#define PCMIN_CTRL1 0x184 +#define PCMIN1_CTRL0 0x188 +#define PCMIN1_CTRL1 0x18C +#define PCMOUT_CTRL0 0x1C0 +#define PCMOUT_CTRL1 0x1C4 +#define PCMOUT_CTRL2 0x1C8 +#define PCMOUT_CTRL3 0x1CC +#define PCMOUT1_CTRL0 0x1D0 +#define PCMOUT1_CTRL1 0x1D4 +#define PCMOUT1_CTRL2 0x1D8 +#define PCMOUT1_CTRL3 0x1DC +#define AUDOUT_CTRL 0x200 +#define AUDOUT_CTRL1 0x204 +#define AUDOUT_BUF0_STA 0x208 +#define AUDOUT_BUF0_EDA 0x20C +#define AUDOUT_BUF0_WPTR 0x210 +#define AUDOUT_BUF1_STA 0x214 +#define AUDOUT_BUF1_EDA 0x218 +#define AUDOUT_BUF1_WPTR 0x21C +#define AUDOUT_FIFO_RPTR 0x220 +#define AUDOUT_INTR_PTR 0x224 +#define AUDOUT_FIFO_STS 0x228 +#define AUDOUT1_CTRL 0x240 +#define AUDOUT1_CTRL1 0x244 +#define AUDOUT1_BUF0_STA 0x248 +#define AUDOUT1_BUF0_EDA 0x24C +#define AUDOUT1_BUF0_WPTR 0x250 +#define AUDOUT1_BUF1_STA 0x254 +#define AUDOUT1_BUF1_EDA 0x258 +#define AUDOUT1_BUF1_WPTR 0x25C +#define AUDOUT1_FIFO_RPTR 0x260 +#define AUDOUT1_INTR_PTR 0x264 +#define AUDOUT1_FIFO_STS 0x268 +#define AUDIN_HDMI_MEAS_CTRL 0x280 +#define AUDIN_HDMI_MEAS_CYCLES_M1 0x284 +#define AUDIN_HDMI_MEAS_INTR_MASKN 0x288 +#define AUDIN_HDMI_MEAS_INTR_STAT 0x28C +#define AUDIN_HDMI_REF_CYCLES_STAT_0 0x290 +#define AUDIN_HDMI_REF_CYCLES_STAT_1 0x294 +#define AUDIN_HDMIRX_AFIFO_STAT 0x298 +#define AUDIN_FIFO0_PIO_STS 0x2C0 +#define AUDIN_FIFO0_PIO_RDL 0x2C4 +#define AUDIN_FIFO0_PIO_RDH 0x2C8 +#define AUDIN_FIFO1_PIO_STS 0x2CC +#define AUDIN_FIFO1_PIO_RDL 0x2D0 +#define AUDIN_FIFO1_PIO_RDH 0x2D4 +#define AUDIN_FIFO2_PIO_STS 0x2D8 +#define AUDIN_FIFO2_PIO_RDL 0x2DC +#define AUDIN_FIFO2_PIO_RDH 0x2E0 +#define AUDOUT_FIFO_PIO_STS 0x2E4 +#define AUDOUT_FIFO_PIO_WRL 0x2E8 +#define AUDOUT_FIFO_PIO_WRH 0x2EC +#define AUDOUT1_FIFO_PIO_STS 0x2F0 /* Unknown */ +#define AUDOUT1_FIFO_PIO_WRL 0x2F4 /* Unknown */ +#define AUDOUT1_FIFO_PIO_WRH 0x2F8 /* Unknown */ +#define AUD_RESAMPLE_CTRL0 0x2FC +#define AUD_RESAMPLE_CTRL1 0x300 +#define AUD_RESAMPLE_STATUS 0x304 + +#endif /* _AUDIN_REGS_H_ */