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-rw-r--r--libc/sysdeps/linux/mips/Makefile.arch6
-rw-r--r--libc/sysdeps/linux/mips/clone.S2
-rw-r--r--libc/sysdeps/linux/mips/sys/asm.h16
3 files changed, 23 insertions, 1 deletions
diff --git a/libc/sysdeps/linux/mips/Makefile.arch b/libc/sysdeps/linux/mips/Makefile.arch
index da5ca1e0f..8edd83516 100644
--- a/libc/sysdeps/linux/mips/Makefile.arch
+++ b/libc/sysdeps/linux/mips/Makefile.arch
@@ -7,9 +7,13 @@
CSRC := \
__longjmp.c brk.c setjmp_aux.c mmap.c __syscall_error.c \
- cacheflush.c pread_write.c sysmips.c _test_and_set.c sigaction.c \
+ cacheflush.c pread_write.c sysmips.c _test_and_set.c \
readahead.c posix_fadvise.c posix_fadvise64.c
+ifneq ($(UCLIBC_HAS_THREADS_NATIVE),y)
+CSRC += sigaction.c
+endif
+
SSRC := bsd-_setjmp.S bsd-setjmp.S setjmp.S clone.S syscall.S pipe.S
ARCH_HEADERS := sgidefs.h
diff --git a/libc/sysdeps/linux/mips/clone.S b/libc/sysdeps/linux/mips/clone.S
index 716cd993f..40caf18e0 100644
--- a/libc/sysdeps/linux/mips/clone.S
+++ b/libc/sysdeps/linux/mips/clone.S
@@ -125,3 +125,5 @@ __thread_start:
move a0,v0
jal HIDDEN_JUMPTARGET(_exit)
.end __thread_start
+weak_alias(clone, __clone)
+
diff --git a/libc/sysdeps/linux/mips/sys/asm.h b/libc/sysdeps/linux/mips/sys/asm.h
index 76f6af3e1..a339f7de3 100644
--- a/libc/sysdeps/linux/mips/sys/asm.h
+++ b/libc/sysdeps/linux/mips/sys/asm.h
@@ -470,4 +470,20 @@ symbol = value
# define MTC0 dmtc0
#endif
+/* The MIPS archtectures do not have a uniform memory model. Particular
+ platforms may provide additional guarantees - for instance, the R4000
+ LL and SC instructions implicitly perform a SYNC, and the 4K promises
+ strong ordering.
+
+ However, in the absence of those guarantees, we must assume weak ordering
+ and SYNC explicitly where necessary.
+
+ Some obsolete MIPS processors may not support the SYNC instruction. This
+ applies to "true" MIPS I processors; most of the processors which compile
+ using MIPS I implement parts of MIPS II. */
+
+#ifndef MIPS_SYNC
+# define MIPS_SYNC sync
+#endif
+
#endif /* sys/asm.h */