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| author | Khem Raj <kraj@mvista.com> | 2008-06-27 04:01:29 +0000 |
|---|---|---|
| committer | Khem Raj <kraj@mvista.com> | 2008-06-27 04:01:29 +0000 |
| commit | d3f9546960f56c05624e2932a899db7f1d38a480 (patch) | |
| tree | 6c63cec6c57ad8060a4b6ef983b3b24ece5fc87c /libc/sysdeps/linux/mips/sys/asm.h | |
| parent | da3e789d079c47fea519270269e0c63dd5d497e2 (diff) | |
| download | uClibc-alpine-d3f9546960f56c05624e2932a899db7f1d38a480.tar.bz2 uClibc-alpine-d3f9546960f56c05624e2932a899db7f1d38a480.tar.xz | |
Sync build machinery stuff from trunk. Some more fixed for mips nptl port
Diffstat (limited to 'libc/sysdeps/linux/mips/sys/asm.h')
| -rw-r--r-- | libc/sysdeps/linux/mips/sys/asm.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/libc/sysdeps/linux/mips/sys/asm.h b/libc/sysdeps/linux/mips/sys/asm.h index 76f6af3e1..4c8bd9cb2 100644 --- a/libc/sysdeps/linux/mips/sys/asm.h +++ b/libc/sysdeps/linux/mips/sys/asm.h @@ -469,5 +469,20 @@ symbol = value # define MFC0 dmfc0 # define MTC0 dmtc0 #endif +/* The MIPS archtectures do not have a uniform memory model. Particular + platforms may provide additional guarantees - for instance, the R4000 + LL and SC instructions implicitly perform a SYNC, and the 4K promises + strong ordering. + + However, in the absence of those guarantees, we must assume weak ordering + and SYNC explicitly where necessary. + + Some obsolete MIPS processors may not support the SYNC instruction. This + applies to "true" MIPS I processors; most of the processors which compile + using MIPS I implement parts of MIPS II. */ + +#ifndef MIPS_SYNC +# define MIPS_SYNC sync +#endif #endif /* sys/asm.h */ |