blob: 8cdcac5560a8e82c1b3cba743079b488a997043e (
plain)
| 1
2
3
4
 | /*  4 instruction cycles not accessing cache and TLB are needed after
    trapa instruction to avoid an SH-4 silicon bug.  */
#define NEED_SYSCALL_INST_PAD
#include <sysdeps/unix/sysv/linux/sh/lowlevellock.h>
 |